Memory devices are typically provided as internal storage areas in computers. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.
One type of memory is a non-volatile memory known as flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that can be erased and reprogrammed in blocks. Many modern personal computers (PCs) have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized and to provide the ability to remotely upgrade the device for enhanced features.
A typical flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed on an individual basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge on the floating gate.
Memory devices are typically formed as semiconductor devices on semiconductor substrates using semiconductor fabrication methods and may include a memory array portion that includes the array of memory cells disposed on the substrate and a periphery that may include logic devices disposed on the substrate, e.g., of row access circuitry and column access circuitry of the memory device.
For some applications, the layers for forming the memory devices in the memory array portion are formed overlying the substrate. The memory array portion is then patterned to form the individual memory cells. Then, the array junctions are implanted in the array portion. The layers for forming the logic devices on the periphery are formed overlying the substrate and are patterned for forming the logic devices of the periphery. However, this often requires forming a relatively thick mask layer, e.g., greater than about 5000 angstroms, overlying the array portion and the periphery to protect the array portion as the logic devices are defined in the periphery. One problem with using such thick mask layers is that it is hard to maintain critical dimensions of the pattern. Another problem with using such thick mask layers is that the resist tends to topple or fall over due to stresses that form during the formation of the logic devices on the periphery.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives for forming peripheries of semiconductor devices.